The present invention relates to methods for the manufacture of semiconductor devices. In particular, the methods involve forming multiple gate oxide thicknesses during the fabrication of integrated circuits for system on a chip (SOC) technology and for embedded DRAM technology.
Complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) technology involves the formation of n-channel FETs (NMOS) and p-channel FETs (PMOS) to form low current and high performance integrated circuits. These devices contain a substrate having various electrically isolated active areas that are separated by regions of insulating material such as shallow trench isolation (STI) features or field oxide isolation (FOX). A gate oxide which is normally silicon dioxide is grown on the substrate in active areas and then a polysilicon gate electrode is formed on the gate oxide. Ion implantation is then typically used to form source/drain regions in the substrate adjacent to the channel which is below the electrode and gate oxide. For example, boron can be implanted to form p-channels and arsenic can be implanted to form n-channels. The final steps in the process of forming the device consist of depositing an insulating layer on the substrate and forming contacts to the source/drain regions and to the gate electrodes.
The thickness of the gate oxide is critical to the performance of the device. There is a constant need for thinner oxides to allow a higher speed device with lower power consumption. Current technology requires gate oxide thicknesses of about 50 Angstroms or less, One concern associated with a thin gate oxide is that it will not be thick enough to prevent migration of impurities such as boron dopant from occurring between the gate electrode and channel regions which will degrade the device performance. U.S. Pat. No. 6,197,647 describes a method of depositing a thin gate oxide thickness of 5 to 15 Angstroms followed by deposition of a polysilicon layer that contains nitrogen to inhibit the migration of impurities across the gate oxide layer.
For ultra thin silicon dioxide gates, leakage current will increase tremendously as thickness is reduced. This will cause a large current in the standby mode (lOFF) and a large standby power consumption, thereby making products with these devices commercially unacceptable.
Another concern associated with thin gate oxides is that an excessively high voltage applied to the gate electrode can cause a gate breakdown resulting in a short circuit between the gate electrode and source region. A thicker gate oxide will allow a higher breakdown voltage but at the expense of a slower speed for the circuit. To partially alleviate the thickness requirement, a dual gate oxide technology has been developed that consists of thicker oxides in circuits such as I/O applications where higher speed is not needed. A higher voltage of about 5 V can be applied and the thicker oxide will provide good reliability. A second gate oxide thickness that is thinner than the first is used to form integrated circuits that require high speed. These circuits typically operate at a lower voltage of about 2 V.
U.S. Pat. No. 6,261,972 mentions that dual oxide thicknesses can be formed by means of a nitridation of the substrate in active areas where growth of a thinner oxide thickness is desired. The two different oxide thicknesses are grown simultaneously in the same chamber because growth on the nitrogen implant d active area is retarded compared to growth on an active ar a without a nitrogen implant. A drawback to this approach is that after nitrogen is introduced into the active channel region in the silicon substrate, significant mobility degradation occurs. U.S. Pat. Nos. 6,080,682 and 6,232,244 also involve nitridation of a substrate and deposition of a blocking layer to prevent loss of nitrogen during a subsequent annealing process in formation of dual gate oxide thicknesses. Nitridation also has a negative impact on the quality of the silicon interface with silicon dioxide.
In U.S. Pat. No. 6,171,911, a method of forming a dual gate oxide is described. Gate oxides are formed in separate steps and a second thinner oxide thickness is grown after removing a previous thicker growth in regions where a thinner thickness is desired. Another feature of this patent is that the annealing step is performed in a hydrogen atmosphere to reduce the native oxide thickness and improve its quality. A native oxide of 10 Angstroms or less generally forms on a substrate if the surface is exposed to air. Contaminants are removed in the annealing process and the layer is densified from about 10 Angstroms to about 4 Angstroms with improved uniformity.
Oxides are generally grown in a thermal oxidation furnace using a dry oxygen ambient at a temperature of between 600xc2x0 C. and 800xc2x0 C. Other methods of forming thin thermal oxides are by RTO (rapid thermal oxidation) or by ISSG (in-situ steam generation).
With the introduction of system on a chip (SOC) technology, there is a need to form multiple gate oxide thicknesses on a substrate to enable the fabrication of multiple circuits with diff rent functions that can all perform at once. For example, circuits for I/O connections with a relatively thick gate oxide of about 50 Angstroms, circuits for high speed devices with a relatively thin gate oxide thickness of about 20 Angstroms and circuits for low power devices with intermediate gate oxide thicknesses are required to operate simultaneously on a substrate. In some cases, more than three different oxide thicknesses may be necessary. Methods of generating more than two oxide thicknesses usually require etch back of unwanted oxide regions resulting in undesirable STI corner loss. Moreover, a large gate leakage is observed on the thinnest oxides. Therefore, an improved method of making multiple gate oxide thicknesses is needed. The improved method should minimize STI corner loss caused by etching, lower the leakage current for thin oxide layers, and prevent boron mobility between the gate electrode and underlying channel. An improved process will also avoid nitridation of a silicon substrate that leads to a poor silicon/silicon oxide interface and reduced ion mobility.
A recent technology called embedded DRAM or e-DRAM involves a combination of memory and logic functions on a chip. Memory circuits require an effective gate oxide thickness of about 50 Angstroms while low power circuits require an effective gate oxide thickness of 12 to 15 Angstroms and high performance circuits need an effective gate oxide thickness in the range of 8 to 12 Angstroms. Traditional ultra-thin silicon dioxide gates are unacceptable because of a high leakage current and a high mobility of doped impurities such as boron between the gate electrode and channel regions. Therefore, an improved method of making e-DRAM devices is needed so that higher performance can be combined with high reliability to satisfy the demand of new technologies.
An objective of the present invention is to provide a method of forming multiple gate oxide thicknesses during the fabrication of a semiconductor device, micro-electromechanical (MEMS) device, or other device requiring the formation of patterned features on a substrate. Preferably the method will provide a lower effective gate oxide thickness so that a thickness sufficient to prevent gate breakdown can be maintained while improving the performance or speed of the device.
A further objective of the present invention is to provide a method of forming multiple gate oxide thicknesses that prevent mobile impurities, especially boron, from migrating between the gate electrode and channel regions of the transistor.
A still further objective of the present invention is to provide a method of forming multiple gate oxide thicknesses that has little or no effect on the integrity of the STI regions in the device, especially minimizing corner rounding that occurs with etch back methods.
A still further objective is to reduce the leakage current across the thin gate oxide layers in the resulting MOSFET to avoid degradation in device performance.
These objectives are achieved by first providing a substrate with active areas separated by regions of insulating material such as STI features. In the first embodiment where a triple oxide thickness is generated, a first layer of silicon dioxide is grown on the active areas. Some regions of the oxide layer are selectively removed by patterning a photoresist layer on the substrate and then etching away the oxide that has been exposed through openings in the photoresist layer. The photoresist is stripped and a second oxide layer is grown on the active areas. The second oxide layer is thinner than the first oxide layer and the second growth adds to the oxide thickness in first growth areas that have not been removed by etching. In first growth regions where the oxide was previously removed by etching, the second growth forms a thinner oxide thickness than was removed by the previous etch. A photoresist is then patterned on the substrate to selectively expose some of the second growth regions. A plasma nitridation is performed which introduces nitrogen into the second growth oxide regions that are uncovered in the photoresist pattern. The nitridation reduces the effective oxide thickness of the second growth gate oxide relative to second growth regions that are not subjected to nitridation. The photoresist is stripped and the substrate is ready for further processing. An annealing step can be performed to remove moisture and contaminants from the substrate and to density the gate oxides into more uniform layers. As a result, there are three effective oxide thicknesses formed. The thinnest oxide layer contains nitrogen which prevents mobile impurities such as boron from migrating between the underlying channel and the gate electrode once the device fabrication is complete. Another advantage is that the number of etch steps has been reduced from two in prior art to one. This reduces the corner rounding damage to the STI features.
In a second embodiment, multiple oxide layers involving four different oxide thicknesses are generated. The first embodiment is followed to the point where a photoresist is selectively patterned over the first and second oxide growth regions. In this case, some of both first and second growth regions are uncovered by the photoresist pattern. Nitridation of the uncovered first and second oxide growth regions reduces the effective oxide thickness in these areas relative to the first and second oxide growth regions that are protected by photoresist. The photoresist layer is then removed, and the substrate is cleaned and annealed. The substrate is ready for subsequent processing in which the gate electrode and source/drain regions are formed. As a result, there are four different effective gate oxide thicknesses on the substrate which can be used to form different types of circuits. Nitridation of two of the four gate oxides helps to prevent boron migration through the gate oxide and reduces leakage of standby current through the gate oxide in the final device. The number of etch steps has been reduced from two in prior art to one which minimizes damage to STI features.
In a third embodiment, multiple oxide layers involving four different oxide thicknesses are generated. The previous embodiment is followed to the point where the etch step after the first oxide growth is shortened so that about 20 Angstroms of first growth oxide remains in regions that are uncovered in the photoresist pattern. This reduces the etching effect on the STI features such that little or no corner rounding occurs. After the photoresist is stripped, another photoresist pattern is formed to selectively expose some of first oxide growth regions that were not reduced in thickness by etch and some first oxide growth regions that were thinned to 20 Angstroms by the etch. Nitridation of the uncovered oxide regions reduces the effective oxide thickness in these areas. The second photoresist layer is then stripped and the substrate is cleaned and annealed. As a result, four different effective oxide thicknesses have been generated on the same substrate that can be used to form four different types of circuits, including I/O, low power, and high performance circuits on the same chip for SOC technology applications. Two of the gate oxides have nitrogen implants that prevent boron migration between the gate electrode and channel regions and reduce leakage of standby current through the gate.
In a fourth embodiment, triple gate oxide layers involving three different oxide thicknesses are generated. A thin RTO oxide is grown on all active regions including one DRAM and two logic regions of the substrate and then HfO2 is deposited. This is a higher k dielectric material than silicon dioxide and reduces the effective oxide thickness and thereby improves performance for a given physical thickness of oxide layer. The oxide is selectively removed from logic regions and a RTO oxide is grown on the active regions. The growth on the high performance active region is retarded because of a previous nitrogen implant. Plasma nitridation is then performed on all gate oxide layers followed by an annealing process. As a result, the hafnium oxide/silicate formed on the DRAM region lowers the effective oxide thickness compared to silicon dioxide which essentially means that the same physical oxide thickness can be maintained to prevent gate breakdown while providing a higher circuit speed that is normally realized only with a thinner thickness. The higher k dielectric material in the gate oxide provides a lower effective oxide thickness. Since all gate oxide regions have nitrogen implants, resistance to boron migration between gate electrode and channel regions has been improved and leakage of standby current is reduced. The method involves only one etch to minimize the effect on STI corners. In this manner, a device for e-DRAM applications can be fabricated which contains DRAM circuits in addition to low power and high performance logic circuits.